In the case of a quad flat no-lead (QFN) package manufacturing process that molds a plurality of packages together and that requires the semiconductor chips to be die-bonded by use of a high melting point solder such as AuSn eutectic solder, the chips are usually subjected to elevated temperature for a long time using a heater.
Specifically, the semiconductor chips are exposed to high temperature conditions until their die boding is complete. Therefore, during this die bonding process, the solder as the bonding material is in a liquid state and hence rapidly diffuses. If this diffusion proceeds extremely, the solder may reach the base material of the lead frames beyond the barrier metal, for example. This results in formation of voids within the solder layer, leading to a reduction in the bonding strength and an increase in the thermal resistance.
A conventional method for preventing the solder from diffusing to the base material of the frames is to limit the number of chips that can be die-bonded at one time and thereby reduce the die bonding time. However, this leads to a great reduction in the number of lead frames that can be obtained per unit volume of the material, resulting in increased material cost (see, e.g., Japanese Patent Laid-Open No. 06-007990).
A QFN package manufacturing process that molds a plurality of packages together currently includes a die bonding process in which the semiconductor chips are subjected to high temperature conditions for a long time. During this die bonding process, the solder layer for bonding the semiconductor chips is exposed to elevated temperature and hence is in a liquid state until a predetermined number of chips are die-bonded. When the solder is in a liquid state, it rapidly forms an inter-metallic compound, since its diffusion rate is very high between metals.
For example, assume that the back side of the semiconductor chip is composed of Ni/Au, the lead frame side is composed of Cu/Ni/Au, and a solder composed of AuSn is used as the die bonding material. In this case, the solder of AuSn forms an inter-metallic compound of Sn—Ni with Ni included in the semiconductor side and in the lead frame side.
However, when the solder of AuSn is in a liquid state as described above, the formation of the inter-metallic compound rapidly proceeds. Therefore, the solder diffuses to the base material Cu of the lead frame through the Ni plating. As a result, voids corresponding to the volume of the solder that has diffused to the Cu base material are formed within the solder layer, resulting in an increase in the thermal resistance of the semiconductor chip and a large reduction in the bonding strength.
FIGS. 9 and 10 illustrate these problems. Specifically, FIG. 9 shows the structure of a conventional semiconductor chip. Referring to FIG. 9, reference numeral 1 denotes GaAs, 2 denotes Ni, and 3 denotes Au. FIG. 10, on the other hand, shows a vertical cross-sectional view of a package in which the semiconductor chip shown in FIG. 9 is die-bonded to a lead frame through application of excessive heat. Referring to FIG. 10, reference numeral 4 denotes a solder formed of AuSn, 5 denotes voids, and 6 denotes the lead frame. Thus, in a conventional soldering method, voids are formed within the solder layer, resulting in reduction in the bonding strength and an increase in the thermal resistance.